1. Field of the Invention:
The present invention relates generally to a structure and process which reduces mechanical stresses imparted to a semiconductor die due to coefficient of expansion mismatch when a plastic encapsulated package fabricated at an elevated temperature is cooled down to room temperature. More particularly, it relates to such a structure and process which reduces the mechanical stresses imparted to the semiconductor die by the plastic encapsulating material.
2. Description of the Prior Art:
It is known in a variety of applications to reduce mechanical stresses between dissimilar materials bonded together at elevated temperatures and then cooled to room temperature by interposing a stress reduction layer of a third material, matching the coefficient of thermal expansion of one of the materials, between the dissimilar materials. In particular, U.S. Pat. No. 4,320,412, issued Mar. 16, 1982 to Hynes et al. discloses the use of an iron-nickel-cobalt Kovar alloy as an intermediate layer between a silicon power transistor die and a copper lead frame including a receptacle for the silicon die for overcoming coefficient of expansion mismatch between the power transistor die and the lead frame. In that environment, the difference in expansion of the copper compared with the silicon may cause sufficient stress during thermal cycling to break the power transistor die.
While such an intermediate layer will overcome the coefficient of expansion mismatch between the silicon and the copper, an even more significant source of mechanical stress on a plastic encapsulated semiconductor integrated circuit die as conventionally packaged arises from shrinkage and contraction of the epoxy or other plastic encapsulating material when it is cured at an elevated temperature and cooled to room temperature. In fact, as discussed more fully below, the mechanical stresses on the semiconductor integrated circuit die which arise from this source are large enough both to cancel out the mechanical stresses arising from the coefficient of expansion difference between silicon and copper and to induce a larger mechanical stress opposite to that induced by the expansion differences of the silicon and copper. Experience with ceramic packages, in which no plastic encapsulating material is used, show that the mechanical stresses induced by the coefficient of expansion difference between a copper bonding pad and a semiconductor integrated circuit die are low enough that most typical integrated circuits require no intermediate layer or other structure to reduce these stresses in ceramic packages. However, in the case of plastic encapsulated integrated circuit packages, the larger mechanical stresses arising from the interaction of the encapsulating material and the integrated circuit die result in a significant number of packaged integrated circuits that fail to meet performance specifications.